Efficient architectures for 3D HWT using dynamic partial reconfiguration
This paper presents the design and implementation of three dimensional (3D) Haar wavelet transform (HWT) with transpose based computation and dynamic partial reconfiguration (DPR) mechanism on field programmable gate array (FPGA). Due to the separability property of the multi-dimensional HWT, the pr...
| Main Authors: | , , , |
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| Format: | Article |
| Published: |
Elsevier North-Holland, Inc.
2010
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| Subjects: | |
| Online Access: | http://dx.doi.org/10.1016/j.sysarc.2010.02.001 http://dx.doi.org/10.1016/j.sysarc.2010.02.001 |