An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores
This paper describes a dynamic partial reconfiguration (DPR) design flow and environment for image and signal processing algorithms used in adaptive applications. Based on the evaluation of the existing DPR design flow, important features such as overall flexibility, application and standardised interfa...
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Published: |
Elsevier Ltd.
2010
|
| Subjects: | |
| Online Access: | http://eprints.uthm.edu.my/3045/ |