High-Performance CMOS Clock And Data Recovery Circuit

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High-Performance CMOS Clock And Data Recovery Circuit

In this dissertation, the design of a 5Gb/s CDR circuit in Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.18 -1.8V standard CMOS process based on a linear half-rate linear architecture is presented. Half-rate architecture allows a voltage controlled oscillator (VCO) to run at one-half of it...

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Bibliographic Details
Main Author:	Tan, Kok Siang
Format:	Thesis
Published:	2006
Subjects:	QA76.75-76.765 Computer software
Online Access:	http://shdl.mmu.edu.my/1094/

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