Design of a floating point unit for 32-bit 5 stage pipeline processor

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Design of a floating point unit for 32-bit 5 stage pipeline processor

This project is about the design of a Floating Point Unit (FPU), integrate the FPU into RISC32 processor and synthesize the FPU design on Field Programmable Gate Array (FPGA). The standalone FPU has been modeled by a senior student in Universiti Tunku Abdul Rahman, Liu Hing Yun. However, there was n...

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Bibliographic Details
Main Author:	Low, Wai Hau
Format:	Final Year Project / Dissertation / Thesis
Published:	2020
Subjects:	T Technology (General) TA Engineering (General). Civil engineering (General)
Online Access:	http://eprints.utar.edu.my/3829/ http://eprints.utar.edu.my/3829/1/16ACB05712_FYP.pdf

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