Design of a floating point unit for 32-bit 5 stage pipeline processor
This project is about the design of a Floating Point Unit (FPU), integrate the FPU into RISC32 processor and synthesize the FPU design on Field Programmable Gate Array (FPGA). The standalone FPU has been modeled by a senior student in Universiti Tunku Abdul Rahman, Liu Hing Yun. However, there was n...
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| Format: | Final Year Project / Dissertation / Thesis |
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2020
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| Online Access: | http://eprints.utar.edu.my/3829/ http://eprints.utar.edu.my/3829/1/16ACB05712_FYP.pdf |