Design of a floating point unit for 32-bit 5 stage pipeline processor
This project is about the design of a Floating Point Unit (FPU), integrate the FPU into RISC32 processor and synthesize the FPU design on Field Programmable Gate Array (FPGA). The standalone FPU has been modeled by a senior student in Universiti Tunku Abdul Rahman, Liu Hing Yun. However, there was n...
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| Format: | Final Year Project / Dissertation / Thesis |
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2020
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| Online Access: | http://eprints.utar.edu.my/3829/ http://eprints.utar.edu.my/3829/1/16ACB05712_FYP.pdf |
| _version_ | 1848886002008981504 |
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| author | Low, Wai Hau |
| author_facet | Low, Wai Hau |
| author_sort | Low, Wai Hau |
| building | UTAR Institutional Repository |
| collection | Online Access |
| description | This project is about the design of a Floating Point Unit (FPU), integrate the FPU into RISC32 processor and synthesize the FPU design on Field Programmable Gate Array (FPGA). The standalone FPU has been modeled by a senior student in Universiti Tunku Abdul Rahman, Liu Hing Yun. However, there was no integration test made on the FPU to the processor and the aforesaid FPU can only perform operation on single precision numbers. Hence, this project is required to develop a FPU which can perform operation on both single and double precision numbers. The development project will start by studying the algorithm of addition on floating point numbers. The addition algorithm is then implemented in the FPU so that the FPU can perform addition on floating point numbers. Also, a dedicated register file is developed for FPU to store 32-bits or 64- bits of data. This project will use top down design methodology: system specification, architecture level and microarchitecture level development. Microarchitecture level will perform unit partitioning of the system and block partitioning of the units. RTL modelling using Verilog will be performed on each block following the units and eventually the complete system. Verification will be made to determine functionality correctness of FPU. The project will integrate the FPU into the RISC32 pipeline processor and the verification will be carried out to prove the functionality of FPU. In the end of this project, the FPU will be synthesized on FPGA. |
| first_indexed | 2025-11-15T19:31:34Z |
| format | Final Year Project / Dissertation / Thesis |
| id | utar-3829 |
| institution | Universiti Tunku Abdul Rahman |
| institution_category | Local University |
| last_indexed | 2025-11-15T19:31:34Z |
| publishDate | 2020 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | utar-38292021-01-06T06:51:56Z Design of a floating point unit for 32-bit 5 stage pipeline processor Low, Wai Hau T Technology (General) TA Engineering (General). Civil engineering (General) This project is about the design of a Floating Point Unit (FPU), integrate the FPU into RISC32 processor and synthesize the FPU design on Field Programmable Gate Array (FPGA). The standalone FPU has been modeled by a senior student in Universiti Tunku Abdul Rahman, Liu Hing Yun. However, there was no integration test made on the FPU to the processor and the aforesaid FPU can only perform operation on single precision numbers. Hence, this project is required to develop a FPU which can perform operation on both single and double precision numbers. The development project will start by studying the algorithm of addition on floating point numbers. The addition algorithm is then implemented in the FPU so that the FPU can perform addition on floating point numbers. Also, a dedicated register file is developed for FPU to store 32-bits or 64- bits of data. This project will use top down design methodology: system specification, architecture level and microarchitecture level development. Microarchitecture level will perform unit partitioning of the system and block partitioning of the units. RTL modelling using Verilog will be performed on each block following the units and eventually the complete system. Verification will be made to determine functionality correctness of FPU. The project will integrate the FPU into the RISC32 pipeline processor and the verification will be carried out to prove the functionality of FPU. In the end of this project, the FPU will be synthesized on FPGA. 2020-05-15 Final Year Project / Dissertation / Thesis NonPeerReviewed application/pdf http://eprints.utar.edu.my/3829/1/16ACB05712_FYP.pdf Low, Wai Hau (2020) Design of a floating point unit for 32-bit 5 stage pipeline processor. Final Year Project, UTAR. http://eprints.utar.edu.my/3829/ |
| spellingShingle | T Technology (General) TA Engineering (General). Civil engineering (General) Low, Wai Hau Design of a floating point unit for 32-bit 5 stage pipeline processor |
| title | Design of a floating point unit for 32-bit 5 stage pipeline processor |
| title_full | Design of a floating point unit for 32-bit 5 stage pipeline processor |
| title_fullStr | Design of a floating point unit for 32-bit 5 stage pipeline processor |
| title_full_unstemmed | Design of a floating point unit for 32-bit 5 stage pipeline processor |
| title_short | Design of a floating point unit for 32-bit 5 stage pipeline processor |
| title_sort | design of a floating point unit for 32-bit 5 stage pipeline processor |
| topic | T Technology (General) TA Engineering (General). Civil engineering (General) |
| url | http://eprints.utar.edu.my/3829/ http://eprints.utar.edu.my/3829/1/16ACB05712_FYP.pdf |