High Frequency Signaling Analysis Of Inter-Chip Package Routing For Multi-Chip Package
Multi-Chip Package (MCP) is becoming a customary form of integration in many high performance and advanced electronic devices. The vast adoptions of this technology are mainly contributed by the advantages for instance lower power consumption, heterogeneous integration of multiple silicon process te...
| Main Author: | Yong, Khang Choong |
|---|---|
| Format: | Thesis |
| Language: | English |
| Published: |
2013
|
| Subjects: | |
| Online Access: | http://eprints.usm.my/45230/ http://eprints.usm.my/45230/1/Yong%20Khang%20Choong24.pdf |
Similar Items
Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging
by: Tan , Ai Heong
Published: (2015)
by: Tan , Ai Heong
Published: (2015)
Simulation On Chip Scale Packaging
by: Dorai Raj, Nanthakumar
Published: (2000)
by: Dorai Raj, Nanthakumar
Published: (2000)
Improvement of Powermite Package Crack and Chip Die Process Optimization Study in Die Attach and Molding Process
by: Nur Afiqqa Rashid,
Published: (2019)
by: Nur Afiqqa Rashid,
Published: (2019)
Electrostatic Discharge For Sysyem On Chip Applications
by: Yuet, Cheryl She Siew
Published: (2017)
by: Yuet, Cheryl She Siew
Published: (2017)
Solder Joint Reliability Of Flip Chip BGA Package
by: Lee, Kor Oon
Published: (2004)
by: Lee, Kor Oon
Published: (2004)
Numerical Analysis During Encapsulation Process Of Molded Underfill With Multi Flip Chip Package
by: Azmi, Muhammad Afiq
Published: (2018)
by: Azmi, Muhammad Afiq
Published: (2018)
Pressure contact multi-chip packaging of SiC
Schottky diodes
by: Gonzalez, Jose Ortiz, et al.
Published: (2017)
by: Gonzalez, Jose Ortiz, et al.
Published: (2017)
Design and Modeling of On-Chip Planar Capacitor for Radio Frequency Application
by: Mohd. Noor, Mariyatul Qibthiyah, et al.
Published: (2006)
by: Mohd. Noor, Mariyatul Qibthiyah, et al.
Published: (2006)
Clock Distribution Network Building Algorithm For Multiple Ips In System On A Chip
by: Tan , Tze Liang
Published: (2017)
by: Tan , Tze Liang
Published: (2017)
Low parasitic inductance multi-chip SiC devices packaging technology
by: Li, Jianfeng, et al.
Published: (2016)
by: Li, Jianfeng, et al.
Published: (2016)
Co-design/simulation of flip-chip assembly for high voltage IGBT packages
by: Rajaguru, P., et al.
Published: (2017)
by: Rajaguru, P., et al.
Published: (2017)
Lead Electromigration In Flip Chip Packaging Under Hast Environment
by: Wong, Shaw Hwang
Published: (2004)
by: Wong, Shaw Hwang
Published: (2004)
Influence Of Copper Pillar Bump Structure On Flip Chip Packaging During Reflow Soldering
by: Chong, Jia Jun
Published: (2019)
by: Chong, Jia Jun
Published: (2019)
CFD Simulation Of Underfill Encapsulation Process In Flip Chip Packaging With Various Dispensing
Methods
by: Khor , Chu Yee
Published: (2010)
by: Khor , Chu Yee
Published: (2010)
Design Of Crack Detection System Software For IC Package
Using Blob Analysis And Neural Network.
by: Samad, Rosdiyana, et al.
Published: (2005)
by: Samad, Rosdiyana, et al.
Published: (2005)
Design and Analysis of Broadband High Isolation of
Discrete Packaged PIN Diode SPDT Switch for
Wireless Data Communication
by: Shairi, Noor Azwan, et al.
Published: (2011)
by: Shairi, Noor Azwan, et al.
Published: (2011)
Artificial neural network chip serration frequency model in end milling of medium carbon steel
by: Patwari, Muhammed Anayet Ullah, et al.
Published: (2009)
by: Patwari, Muhammed Anayet Ullah, et al.
Published: (2009)
Timing performance enhance for routing channel in 28NM FPGA chip
by: Kin , Si Kee
Published: (2013)
by: Kin , Si Kee
Published: (2013)
Analysis Of Plastic Encapsulation Process In 3D IC Package With Through-Silicon Via (Tsv) Technology
by: Ong, Ern Seang
Published: (2013)
by: Ong, Ern Seang
Published: (2013)
Network-on-chip implementation of hierarchical torus network
by: Rahman, M.M. Hafizur, et al.
Published: (2013)
by: Rahman, M.M. Hafizur, et al.
Published: (2013)
Comparison of performance of no-clean and water-soluble fluxes in fine-pitch flip-chip package / Saif Wakeel
by: Saif , Wakeel
Published: (2021)
by: Saif , Wakeel
Published: (2021)
Design and modeling of on-chip planar capacitor for RF application
by: Mohd. Noor, Mariyatul Qibthiyah
Published: (2006)
by: Mohd. Noor, Mariyatul Qibthiyah
Published: (2006)
Influence of chip serration frequency on chatter formation during end milling of Ti6Al4V
by: Patwari, Muhammed Anayet Ullah, et al.
Published: (2011)
by: Patwari, Muhammed Anayet Ullah, et al.
Published: (2011)
Effect of Bond Layer Properties to Thermo-Mechanical Stresses in Flip Chip Packaging
by: Pok, Y., et al.
Published: (2017)
by: Pok, Y., et al.
Published: (2017)
A high radix hierarchical interconnection network for network-on-chip
by: N.M. Ali, Mohammed, et al.
Published: (2016)
by: N.M. Ali, Mohammed, et al.
Published: (2016)
Inter-chip communications in an analogue neural network utilising frequency division multiplexing
by: Craven, Michael P.
Published: (1994)
by: Craven, Michael P.
Published: (1994)
System identification software package
by: Ismail, Iza Wanee
Published: (2007)
by: Ismail, Iza Wanee
Published: (2007)
Conducted Electromagnetic Susceptibility Analysis of Chips Based on BCI Method
by: Wen, Zheng, et al.
Published: (2025)
by: Wen, Zheng, et al.
Published: (2025)
Power flow analysis software package using MATLAB
by: Mohamad Isa, Mohd Shahimi
Published: (2007)
by: Mohamad Isa, Mohd Shahimi
Published: (2007)
Impact Of Differential Pair Routing Discontinuities On Signal Integrity In Printed Circuit Board Design
by: Adanan, Omar Mukhtar
Published: (2013)
by: Adanan, Omar Mukhtar
Published: (2013)
Analysis of modulation parameters of high frequency digital modulation signal
by: Anuar, Hardy Azmir
Published: (2004)
by: Anuar, Hardy Azmir
Published: (2004)
Effects of type of packaging material on physicochemical and sensory characteristics of deep-fat-fried banana chips
by: Ammawath, Wanna, et al.
Published: (2002)
by: Ammawath, Wanna, et al.
Published: (2002)
High frequency small signal modeling of CNTFET
by: Farhana, Soheli, et al.
Published: (2013)
by: Farhana, Soheli, et al.
Published: (2013)
An Optical Set-Up For Inspecting Edge Chipping Defects Of Dws Solar Wafer
by: Lim, Thai Li
Published: (2019)
by: Lim, Thai Li
Published: (2019)
Tilt based passive optimizations for microfluidics and lab-on-chip devices - A simulation study
by: Jeroish, Z. E., et al.
Published: (2020)
by: Jeroish, Z. E., et al.
Published: (2020)
Sub-micron technology development and system-on-chip (Soc) design - data compression core
by: Husin, Nasir Sheikh
Published: (2002)
by: Husin, Nasir Sheikh
Published: (2002)
Classification of the marking on integrated circuit chips based on moments and projection profile - a comparison
by: Kartigayan, M., et al.
Published: (2005)
by: Kartigayan, M., et al.
Published: (2005)
Routing techniques in network-on-chip based multiprocessor-system-on-chip for IoT: a systematic review
by: Husin, Nor Azura, et al.
Published: (2024)
by: Husin, Nor Azura, et al.
Published: (2024)
A study on thermal management in electronic packaging components
by: Awang Masri, A.A
Published: (2002)
by: Awang Masri, A.A
Published: (2002)
MATHCAD based printed microwave LPF simulation package
by: Esa, Mazlina, et al.
Published: (2000)
by: Esa, Mazlina, et al.
Published: (2000)
Similar Items
-
Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging
by: Tan , Ai Heong
Published: (2015) -
Simulation On Chip Scale Packaging
by: Dorai Raj, Nanthakumar
Published: (2000) -
Improvement of Powermite Package Crack and Chip Die Process Optimization Study in Die Attach and Molding Process
by: Nur Afiqqa Rashid,
Published: (2019) -
Electrostatic Discharge For Sysyem On Chip Applications
by: Yuet, Cheryl She Siew
Published: (2017) -
Solder Joint Reliability Of Flip Chip BGA Package
by: Lee, Kor Oon
Published: (2004)