New Cdc Design Tool For Analog Layout Workflow
The placement and routing on CMOS analog layout design had always been a time consuming and irritating process due to large amount of transistor devices placements, arrangements and a lot of critical nets routing constraint. Manual efforts to complete analog layout design took few weeks to months’ t...
| Main Author: | |
|---|---|
| Format: | Thesis |
| Language: | English |
| Published: |
2015
|
| Subjects: | |
| Online Access: | http://eprints.usm.my/40966/ http://eprints.usm.my/40966/1/NG_HIN_MUNG_24_pages.pdf |