APA (7th ed.) Citation

H. Salih, M., & Arshad, M. R. (2010). Embedded Parallel Systolic Architecture For Multi-Filtering Techniques Using FPGA.

Chicago Style (17th ed.) Citation

H. Salih, Muataz, and M. R. Arshad. Embedded Parallel Systolic Architecture For Multi-Filtering Techniques Using FPGA. 2010.

MLA (9th ed.) Citation

H. Salih, Muataz, and M. R. Arshad. Embedded Parallel Systolic Architecture For Multi-Filtering Techniques Using FPGA. 2010.