Embedded Parallel Systolic Architecture For Multi-Filtering Techniques Using FPGA.
Computing systems typically suffer from delay in data processing.
| Main Authors: | , |
|---|---|
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2010
|
| Subjects: | |
| Online Access: | http://eprints.usm.my/21979/ http://eprints.usm.my/21979/1/T380.pdf |