Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation
Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circui...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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Institute of Advanced Engineering and Science
2020
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| Online Access: | http://psasir.upm.edu.my/id/eprint/87021/ http://psasir.upm.edu.my/id/eprint/87021/1/Optimized%20low%20voltage%20low%20power%20dynamic%20comparator.pdf |
| _version_ | 1848860345440927744 |
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| author | Rusli, Julie Roslita Shafie, Suhaidi Mohd Sidek, Roslina Abdul Majid, Hasmayadi Wan Hasan, Wan Zuha Mustafa, Mohd. Amrallah |
| author_facet | Rusli, Julie Roslita Shafie, Suhaidi Mohd Sidek, Roslina Abdul Majid, Hasmayadi Wan Hasan, Wan Zuha Mustafa, Mohd. Amrallah |
| author_sort | Rusli, Julie Roslita |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The simulation result show that the proposed comparator circuit achieved significant reduction of power consumption and delay during worst case condition compared to dynamic comparator proposed from previous researchers. |
| first_indexed | 2025-11-15T12:43:46Z |
| format | Article |
| id | upm-87021 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T12:43:46Z |
| publishDate | 2020 |
| publisher | Institute of Advanced Engineering and Science |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-870212022-01-10T08:55:15Z http://psasir.upm.edu.my/id/eprint/87021/ Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation Rusli, Julie Roslita Shafie, Suhaidi Mohd Sidek, Roslina Abdul Majid, Hasmayadi Wan Hasan, Wan Zuha Mustafa, Mohd. Amrallah Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The simulation result show that the proposed comparator circuit achieved significant reduction of power consumption and delay during worst case condition compared to dynamic comparator proposed from previous researchers. Institute of Advanced Engineering and Science 2020-02 Article PeerReviewed text en http://psasir.upm.edu.my/id/eprint/87021/1/Optimized%20low%20voltage%20low%20power%20dynamic%20comparator.pdf Rusli, Julie Roslita and Shafie, Suhaidi and Mohd Sidek, Roslina and Abdul Majid, Hasmayadi and Wan Hasan, Wan Zuha and Mustafa, Mohd. Amrallah (2020) Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation. Indonesian Journal of Electrical Engineering and Computer Science, 17 (2). 783 - 792. ISSN 2502-4752; ESSN: 2502-4760 http://ijeecs.iaescore.com/index.php/IJEECS/article/view/20650 10.11591/ijeecs.v17.i2.pp783-792 |
| spellingShingle | Rusli, Julie Roslita Shafie, Suhaidi Mohd Sidek, Roslina Abdul Majid, Hasmayadi Wan Hasan, Wan Zuha Mustafa, Mohd. Amrallah Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation |
| title | Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation |
| title_full | Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation |
| title_fullStr | Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation |
| title_full_unstemmed | Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation |
| title_short | Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation |
| title_sort | optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation |
| url | http://psasir.upm.edu.my/id/eprint/87021/ http://psasir.upm.edu.my/id/eprint/87021/ http://psasir.upm.edu.my/id/eprint/87021/ http://psasir.upm.edu.my/id/eprint/87021/1/Optimized%20low%20voltage%20low%20power%20dynamic%20comparator.pdf |