Development of A 115V, 400HZ cascaded 41-level inverter
Cascaded multilevel inverters are widely used in various fields, from oil and gas, power supply installations, to power quality devices. While there are many advantages of the cascaded multilevel inverter such as low voltage stress for each switching device and higher power quality, the main drawbac...
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| Format: | Thesis |
| Language: | English |
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2013
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| Online Access: | http://psasir.upm.edu.my/id/eprint/56142/ http://psasir.upm.edu.my/id/eprint/56142/1/FK%202013%2099RR.pdf |
| _version_ | 1848852999349207040 |
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| author | Mohamad, Ahmad Syukri |
| author_facet | Mohamad, Ahmad Syukri |
| author_sort | Mohamad, Ahmad Syukri |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | Cascaded multilevel inverters are widely used in various fields, from oil and gas, power supply installations, to power quality devices. While there are many advantages of the cascaded multilevel inverter such as low voltage stress for each switching device and higher power quality, the main drawback for this type of inverter is the high number of switching device it needs in an installation. In order to reduce total harmonics distortion (THD) of the output voltage waveform, the number of output voltage level need to be increased, hence the higher number of switching devices. This subsequently increases the installation cost, inverter circuit size and power losses – in the form of heat and voltage losses in the inverter circuit, thus compromises the efficiency of the inverter. In this research, a novel cascaded multilevel inverter topology is proposed with a minimum number of switching devices and driver circuits needed. The proposed topology also needs to turn on only three switching devices at any operation time for any output voltage level configurations. The prototype inverter can also be designed to supply a load with a specific power factor requirement. Field-programmable gate array (FPGA) is used to replace large number of logic gate circuits that function is to synthesize the switching signals for the prototype inverter from a single oscillator signal. A Verilog program is created in order for the FPGA to produce the desired switching signals according to the design requirements. The prototype inverter is a single phase 115V, 400Hz 41-level multilevel cascaded inverter designed using the novel cascaded multilevel inverter topology. The prototype inverter is constructed and then tested using resistive and resistive-inductive (RL) loads. In the process, the novel cascaded multilevel inverter topology validity is verified by the simulation and experimental results. The experimental results show that the prototype inverter produces 115V,400Hz output that resembles a clean sinusoidal waveform with THD of around 2.5% to 3.5%,below the required 5% THD limit according to IEEE standards. |
| first_indexed | 2025-11-15T10:47:00Z |
| format | Thesis |
| id | upm-56142 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T10:47:00Z |
| publishDate | 2013 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-561422017-07-18T03:25:03Z http://psasir.upm.edu.my/id/eprint/56142/ Development of A 115V, 400HZ cascaded 41-level inverter Mohamad, Ahmad Syukri Cascaded multilevel inverters are widely used in various fields, from oil and gas, power supply installations, to power quality devices. While there are many advantages of the cascaded multilevel inverter such as low voltage stress for each switching device and higher power quality, the main drawback for this type of inverter is the high number of switching device it needs in an installation. In order to reduce total harmonics distortion (THD) of the output voltage waveform, the number of output voltage level need to be increased, hence the higher number of switching devices. This subsequently increases the installation cost, inverter circuit size and power losses – in the form of heat and voltage losses in the inverter circuit, thus compromises the efficiency of the inverter. In this research, a novel cascaded multilevel inverter topology is proposed with a minimum number of switching devices and driver circuits needed. The proposed topology also needs to turn on only three switching devices at any operation time for any output voltage level configurations. The prototype inverter can also be designed to supply a load with a specific power factor requirement. Field-programmable gate array (FPGA) is used to replace large number of logic gate circuits that function is to synthesize the switching signals for the prototype inverter from a single oscillator signal. A Verilog program is created in order for the FPGA to produce the desired switching signals according to the design requirements. The prototype inverter is a single phase 115V, 400Hz 41-level multilevel cascaded inverter designed using the novel cascaded multilevel inverter topology. The prototype inverter is constructed and then tested using resistive and resistive-inductive (RL) loads. In the process, the novel cascaded multilevel inverter topology validity is verified by the simulation and experimental results. The experimental results show that the prototype inverter produces 115V,400Hz output that resembles a clean sinusoidal waveform with THD of around 2.5% to 3.5%,below the required 5% THD limit according to IEEE standards. 2013-04 Thesis NonPeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/56142/1/FK%202013%2099RR.pdf Mohamad, Ahmad Syukri (2013) Development of A 115V, 400HZ cascaded 41-level inverter. Masters thesis, Universiti Putra Malaysia. Electric inverters Voltage |
| spellingShingle | Electric inverters Voltage Mohamad, Ahmad Syukri Development of A 115V, 400HZ cascaded 41-level inverter |
| title | Development of A 115V, 400HZ cascaded 41-level inverter |
| title_full | Development of A 115V, 400HZ cascaded 41-level inverter |
| title_fullStr | Development of A 115V, 400HZ cascaded 41-level inverter |
| title_full_unstemmed | Development of A 115V, 400HZ cascaded 41-level inverter |
| title_short | Development of A 115V, 400HZ cascaded 41-level inverter |
| title_sort | development of a 115v, 400hz cascaded 41-level inverter |
| topic | Electric inverters Voltage |
| url | http://psasir.upm.edu.my/id/eprint/56142/ http://psasir.upm.edu.my/id/eprint/56142/1/FK%202013%2099RR.pdf |