A low power multiplexer based pass transistor logic full adder
In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP)...
| Main Authors: | , , , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2015
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| Online Access: | http://psasir.upm.edu.my/id/eprint/56112/ http://psasir.upm.edu.my/id/eprint/56112/1/A%20low%20power%20multiplexer%20based%20pass%20transistor%20logic%20full%20adder.pdf |
| _version_ | 1848852990831624192 |
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| author | Kamsani, Noor Ain Thangasamy, Veeraiyah Hashim, Shaiful Jahari Yusoff, Zubaida Bukhori, Muhammad Faiz Hamidon, Mohd Nizar |
| author_facet | Kamsani, Noor Ain Thangasamy, Veeraiyah Hashim, Shaiful Jahari Yusoff, Zubaida Bukhori, Muhammad Faiz Hamidon, Mohd Nizar |
| author_sort | Kamsani, Noor Ain |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10-18 J and its power consumption is 2.01μW. The proposed full adder is also capable to function at lower supply voltages of 0.4 V and 0.8 V without significant performance degradation. The proposed adder when cascaded in a 4-bit ripple carry adder configuration, its power, delay and PDP performance are better than the other adders making it suitable for larger arithmetic circuits. |
| first_indexed | 2025-11-15T10:46:52Z |
| format | Conference or Workshop Item |
| id | upm-56112 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T10:46:52Z |
| publishDate | 2015 |
| publisher | IEEE |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-561122017-07-03T09:36:37Z http://psasir.upm.edu.my/id/eprint/56112/ A low power multiplexer based pass transistor logic full adder Kamsani, Noor Ain Thangasamy, Veeraiyah Hashim, Shaiful Jahari Yusoff, Zubaida Bukhori, Muhammad Faiz Hamidon, Mohd Nizar In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10-18 J and its power consumption is 2.01μW. The proposed full adder is also capable to function at lower supply voltages of 0.4 V and 0.8 V without significant performance degradation. The proposed adder when cascaded in a 4-bit ripple carry adder configuration, its power, delay and PDP performance are better than the other adders making it suitable for larger arithmetic circuits. IEEE 2015 Conference or Workshop Item PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/56112/1/A%20low%20power%20multiplexer%20based%20pass%20transistor%20logic%20full%20adder.pdf Kamsani, Noor Ain and Thangasamy, Veeraiyah and Hashim, Shaiful Jahari and Yusoff, Zubaida and Bukhori, Muhammad Faiz and Hamidon, Mohd Nizar (2015) A low power multiplexer based pass transistor logic full adder. In: 2015 IEEE Regional Symposium on Micro and Nano Electronics (RSM 2015), 19-21 Aug. 2015, Primula Beach Hotel, Kuala Terengganu. . 10.1109/RSM.2015.7354994 |
| spellingShingle | Kamsani, Noor Ain Thangasamy, Veeraiyah Hashim, Shaiful Jahari Yusoff, Zubaida Bukhori, Muhammad Faiz Hamidon, Mohd Nizar A low power multiplexer based pass transistor logic full adder |
| title | A low power multiplexer based pass transistor logic full adder |
| title_full | A low power multiplexer based pass transistor logic full adder |
| title_fullStr | A low power multiplexer based pass transistor logic full adder |
| title_full_unstemmed | A low power multiplexer based pass transistor logic full adder |
| title_short | A low power multiplexer based pass transistor logic full adder |
| title_sort | low power multiplexer based pass transistor logic full adder |
| url | http://psasir.upm.edu.my/id/eprint/56112/ http://psasir.upm.edu.my/id/eprint/56112/ http://psasir.upm.edu.my/id/eprint/56112/1/A%20low%20power%20multiplexer%20based%20pass%20transistor%20logic%20full%20adder.pdf |