A low power multiplexer based pass transistor logic full adder

A low power multiplexer based pass transistor logic full adder

In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP)...

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Bibliographic Details
Main Authors: Kamsani, Noor Ain, Thangasamy, Veeraiyah, Hashim, Shaiful Jahari, Yusoff, Zubaida, Bukhori, Muhammad Faiz, Hamidon, Mohd Nizar
Format: Conference or Workshop Item
Language:English
Published: IEEE 2015
Online Access:http://psasir.upm.edu.my/id/eprint/56112/
http://psasir.upm.edu.my/id/eprint/56112/1/A%20low%20power%20multiplexer%20based%20pass%20transistor%20logic%20full%20adder.pdf

Internet

http://psasir.upm.edu.my/id/eprint/56112/
http://psasir.upm.edu.my/id/eprint/56112/1/A%20low%20power%20multiplexer%20based%20pass%20transistor%20logic%20full%20adder.pdf

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