Co-design/simulation of flip-chip assembly for high voltage IGBT packages
This paper details a co-design and modelling methodology to optimise the flip-chip assembly parameters so that the overall package and system meets performance and reliability specifications for LED lighting applications. A co-design methodology is employed between device level modelling and package...
| Main Authors: | , , , , , , , , , |
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| Format: | Conference or Workshop Item |
| Published: |
2017
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| Online Access: | https://eprints.nottingham.ac.uk/51686/ |
| _version_ | 1848798551768825856 |
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| author | Rajaguru, P. Bailey, Christopher Aliyu, Attahir Murtala Castellazzi, Alberto Pathirana, V. Udugampola, N. Trajkovic, T. Udrea, F. Mitchelson, P.D. Elliot, A.D.T. |
| author_facet | Rajaguru, P. Bailey, Christopher Aliyu, Attahir Murtala Castellazzi, Alberto Pathirana, V. Udugampola, N. Trajkovic, T. Udrea, F. Mitchelson, P.D. Elliot, A.D.T. |
| author_sort | Rajaguru, P. |
| building | Nottingham Research Data Repository |
| collection | Online Access |
| description | This paper details a co-design and modelling methodology to optimise the flip-chip assembly parameters so that the overall package and system meets performance and reliability specifications for LED lighting applications. A co-design methodology is employed between device level modelling and package level modelling in order enhance the flow of information. As part of this methodology, coupled electrical, thermal and mechniacal predictions are made in order to mitigate underfill dielectric breakdown failure and solder interconnect fatigue failure. Five commercial underfills were selected for investigating the trade-off in materials properties that mitigate underfill electrical breakdown and solder joint fatigue. |
| first_indexed | 2025-11-14T20:21:34Z |
| format | Conference or Workshop Item |
| id | nottingham-51686 |
| institution | University of Nottingham Malaysia Campus |
| institution_category | Local University |
| last_indexed | 2025-11-14T20:21:34Z |
| publishDate | 2017 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | nottingham-516862020-05-04T19:08:42Z https://eprints.nottingham.ac.uk/51686/ Co-design/simulation of flip-chip assembly for high voltage IGBT packages Rajaguru, P. Bailey, Christopher Aliyu, Attahir Murtala Castellazzi, Alberto Pathirana, V. Udugampola, N. Trajkovic, T. Udrea, F. Mitchelson, P.D. Elliot, A.D.T. This paper details a co-design and modelling methodology to optimise the flip-chip assembly parameters so that the overall package and system meets performance and reliability specifications for LED lighting applications. A co-design methodology is employed between device level modelling and package level modelling in order enhance the flow of information. As part of this methodology, coupled electrical, thermal and mechniacal predictions are made in order to mitigate underfill dielectric breakdown failure and solder interconnect fatigue failure. Five commercial underfills were selected for investigating the trade-off in materials properties that mitigate underfill electrical breakdown and solder joint fatigue. 2017-09-27 Conference or Workshop Item PeerReviewed Rajaguru, P., Bailey, Christopher, Aliyu, Attahir Murtala, Castellazzi, Alberto, Pathirana, V., Udugampola, N., Trajkovic, T., Udrea, F., Mitchelson, P.D. and Elliot, A.D.T. (2017) Co-design/simulation of flip-chip assembly for high voltage IGBT packages. In: 23rd International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2017, 27-29 September 2018, Amsterdam, Netherlands. https://ieeexplore.ieee.org/document/8233847/ |
| spellingShingle | Rajaguru, P. Bailey, Christopher Aliyu, Attahir Murtala Castellazzi, Alberto Pathirana, V. Udugampola, N. Trajkovic, T. Udrea, F. Mitchelson, P.D. Elliot, A.D.T. Co-design/simulation of flip-chip assembly for high voltage IGBT packages |
| title | Co-design/simulation of flip-chip assembly for high voltage IGBT packages |
| title_full | Co-design/simulation of flip-chip assembly for high voltage IGBT packages |
| title_fullStr | Co-design/simulation of flip-chip assembly for high voltage IGBT packages |
| title_full_unstemmed | Co-design/simulation of flip-chip assembly for high voltage IGBT packages |
| title_short | Co-design/simulation of flip-chip assembly for high voltage IGBT packages |
| title_sort | co-design/simulation of flip-chip assembly for high voltage igbt packages |
| url | https://eprints.nottingham.ac.uk/51686/ https://eprints.nottingham.ac.uk/51686/ |