Low parasitic inductance multi-chip SiC devices packaging technology

This paper presents a novel packaging structure which employs stacked substrate and flexible printed circuit board (PCB) to obtain very low parasitic inductance and hence feature high switching speed SiC power devices. A half-bridge module aimed at blocking voltage up to 2.5kV has been designed to a...

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Main Authors: Li, Jianfeng, Mouawad, Bassem, Castellazzi, Alberto, Friedrichs, Peter, Johnson, Christopher Mark
Format: Conference or Workshop Item
Published: 2016
Subjects:
Online Access:https://eprints.nottingham.ac.uk/37316/
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author Li, Jianfeng
Mouawad, Bassem
Castellazzi, Alberto
Friedrichs, Peter
Johnson, Christopher Mark
author_facet Li, Jianfeng
Mouawad, Bassem
Castellazzi, Alberto
Friedrichs, Peter
Johnson, Christopher Mark
author_sort Li, Jianfeng
building Nottingham Research Data Repository
collection Online Access
description This paper presents a novel packaging structure which employs stacked substrate and flexible printed circuit board (PCB) to obtain very low parasitic inductance and hence feature high switching speed SiC power devices. A half-bridge module aimed at blocking voltage up to 2.5kV has been designed to accommodate 8 SiC JFETs and 4 SiC diodes. Electromagnetic simulation results reveal extremely low inductance values of the major loops. Then the prototyping of the designed package including the assembly process, all the electrical test to evaluate the electrical performance are presented.
first_indexed 2025-11-14T19:32:00Z
format Conference or Workshop Item
id nottingham-37316
institution University of Nottingham Malaysia Campus
institution_category Local University
last_indexed 2025-11-14T19:32:00Z
publishDate 2016
recordtype eprints
repository_type Digital Repository
spelling nottingham-373162020-05-04T17:34:33Z https://eprints.nottingham.ac.uk/37316/ Low parasitic inductance multi-chip SiC devices packaging technology Li, Jianfeng Mouawad, Bassem Castellazzi, Alberto Friedrichs, Peter Johnson, Christopher Mark This paper presents a novel packaging structure which employs stacked substrate and flexible printed circuit board (PCB) to obtain very low parasitic inductance and hence feature high switching speed SiC power devices. A half-bridge module aimed at blocking voltage up to 2.5kV has been designed to accommodate 8 SiC JFETs and 4 SiC diodes. Electromagnetic simulation results reveal extremely low inductance values of the major loops. Then the prototyping of the designed package including the assembly process, all the electrical test to evaluate the electrical performance are presented. 2016-03-01 Conference or Workshop Item PeerReviewed Li, Jianfeng, Mouawad, Bassem, Castellazzi, Alberto, Friedrichs, Peter and Johnson, Christopher Mark (2016) Low parasitic inductance multi-chip SiC devices packaging technology. In: 18th European Conference on Power Electronics and Applications, 5-9 September 2016, Karlsruhe, Germany. Wide bandgap devices High frequency power converter Silicon Carbide (SiC) Packaging high voltage power converters JFET Wind energy
spellingShingle Wide bandgap devices
High frequency power converter
Silicon Carbide (SiC)
Packaging
high voltage power converters
JFET
Wind energy
Li, Jianfeng
Mouawad, Bassem
Castellazzi, Alberto
Friedrichs, Peter
Johnson, Christopher Mark
Low parasitic inductance multi-chip SiC devices packaging technology
title Low parasitic inductance multi-chip SiC devices packaging technology
title_full Low parasitic inductance multi-chip SiC devices packaging technology
title_fullStr Low parasitic inductance multi-chip SiC devices packaging technology
title_full_unstemmed Low parasitic inductance multi-chip SiC devices packaging technology
title_short Low parasitic inductance multi-chip SiC devices packaging technology
title_sort low parasitic inductance multi-chip sic devices packaging technology
topic Wide bandgap devices
High frequency power converter
Silicon Carbide (SiC)
Packaging
high voltage power converters
JFET
Wind energy
url https://eprints.nottingham.ac.uk/37316/