VLSI Design Of A Bit Serial Arithmetic Logic Unit
The arithmetic logic unit (ALU) is designed to perform bit serial operation on two 8 bits input. In this project , a Very High Speed Integrated Circuit Hardware Description Language (VHDL) code is written using the Altera MAX+Plus II environment to design, compile and simulate for each operation in...
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| Format: | Thesis |
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2003
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| Online Access: | http://shdl.mmu.edu.my/966/ |
| _version_ | 1848789670965542912 |
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| author | Lee, Tiong Kiat |
| author_facet | Lee, Tiong Kiat |
| author_sort | Lee, Tiong Kiat |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | The arithmetic logic unit (ALU) is designed to perform bit serial operation on two 8 bits input. In this project , a Very High Speed Integrated Circuit Hardware Description Language (VHDL) code is written using the Altera MAX+Plus II environment to design, compile and simulate for each operation in the bit serial arithmetic logic unit. The details of each design steps from design entry, compilation, debugging, simulation and syntheis is described in this project. |
| first_indexed | 2025-11-14T18:00:25Z |
| format | Thesis |
| id | mmu-966 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:00:25Z |
| publishDate | 2003 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-9662010-07-15T06:38:54Z http://shdl.mmu.edu.my/966/ VLSI Design Of A Bit Serial Arithmetic Logic Unit Lee, Tiong Kiat TK7800-8360 Electronics The arithmetic logic unit (ALU) is designed to perform bit serial operation on two 8 bits input. In this project , a Very High Speed Integrated Circuit Hardware Description Language (VHDL) code is written using the Altera MAX+Plus II environment to design, compile and simulate for each operation in the bit serial arithmetic logic unit. The details of each design steps from design entry, compilation, debugging, simulation and syntheis is described in this project. 2003-04 Thesis NonPeerReviewed Lee, Tiong Kiat (2003) VLSI Design Of A Bit Serial Arithmetic Logic Unit. Masters thesis, Multimedia University. http://myto.perpun.net.my/metoalogin/logina.php |
| spellingShingle | TK7800-8360 Electronics Lee, Tiong Kiat VLSI Design Of A Bit Serial Arithmetic Logic Unit |
| title | VLSI Design Of A Bit Serial Arithmetic Logic Unit |
| title_full | VLSI Design Of A Bit Serial Arithmetic Logic Unit |
| title_fullStr | VLSI Design Of A Bit Serial Arithmetic Logic Unit |
| title_full_unstemmed | VLSI Design Of A Bit Serial Arithmetic Logic Unit |
| title_short | VLSI Design Of A Bit Serial Arithmetic Logic Unit |
| title_sort | vlsi design of a bit serial arithmetic logic unit |
| topic | TK7800-8360 Electronics |
| url | http://shdl.mmu.edu.my/966/ http://shdl.mmu.edu.my/966/ |