VLSI Design Of A Bit Serial Arithmetic Logic Unit
The arithmetic logic unit (ALU) is designed to perform bit serial operation on two 8 bits input. In this project , a Very High Speed Integrated Circuit Hardware Description Language (VHDL) code is written using the Altera MAX+Plus II environment to design, compile and simulate for each operation in...
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| Format: | Thesis |
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2003
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| Online Access: | http://shdl.mmu.edu.my/966/ |