VLSI Design of a Wavelet Processing Core
A processing core architecture for the implementation of the discrete wavelet transform (DWT), optimized for throughput, scalability and programmability is proposed. The architecture is based on the RISC architecture with an instruction set specifically designed to facilitate the implementation of w...
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| Format: | Article |
| Language: | English |
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IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
2006
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| Online Access: | http://shdl.mmu.edu.my/3250/ http://shdl.mmu.edu.my/3250/1/1299.pdf |
| _version_ | 1848790275644719104 |
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| author | Sze, Wei Lee Soon, Chieh Lim |
| author_facet | Sze, Wei Lee Soon, Chieh Lim |
| author_sort | Sze, Wei Lee |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | A processing core architecture for the implementation of the discrete wavelet transform (DWT), optimized for throughput, scalability and programmability is proposed. The architecture is based on the RISC architecture with an instruction set specifically designed to facilitate the implementation of wavelet-based applications and a memory controller optimized for the memory access pattern of DWT processing. |
| first_indexed | 2025-11-14T18:10:02Z |
| format | Article |
| id | mmu-3250 |
| institution | Multimedia University |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-14T18:10:02Z |
| publishDate | 2006 |
| publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-32502014-03-03T04:51:24Z http://shdl.mmu.edu.my/3250/ VLSI Design of a Wavelet Processing Core Sze, Wei Lee Soon, Chieh Lim T Technology (General) QA75.5-76.95 Electronic computers. Computer science A processing core architecture for the implementation of the discrete wavelet transform (DWT), optimized for throughput, scalability and programmability is proposed. The architecture is based on the RISC architecture with an instruction set specifically designed to facilitate the implementation of wavelet-based applications and a memory controller optimized for the memory access pattern of DWT processing. IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC 2006-11 Article NonPeerReviewed text en http://shdl.mmu.edu.my/3250/1/1299.pdf Sze, Wei Lee and Soon, Chieh Lim (2006) VLSI Design of a Wavelet Processing Core. IEEE Transactions on Circuits and Systems for Video Technology, 16 (11). pp. 1350-1361. ISSN 1051-8215 http://dx.doi.org/10.1109/TCSVT.2006.883507 doi:10.1109/TCSVT.2006.883507 doi:10.1109/TCSVT.2006.883507 |
| spellingShingle | T Technology (General) QA75.5-76.95 Electronic computers. Computer science Sze, Wei Lee Soon, Chieh Lim VLSI Design of a Wavelet Processing Core |
| title | VLSI Design of a Wavelet Processing Core |
| title_full | VLSI Design of a Wavelet Processing Core |
| title_fullStr | VLSI Design of a Wavelet Processing Core |
| title_full_unstemmed | VLSI Design of a Wavelet Processing Core |
| title_short | VLSI Design of a Wavelet Processing Core |
| title_sort | vlsi design of a wavelet processing core |
| topic | T Technology (General) QA75.5-76.95 Electronic computers. Computer science |
| url | http://shdl.mmu.edu.my/3250/ http://shdl.mmu.edu.my/3250/ http://shdl.mmu.edu.my/3250/ http://shdl.mmu.edu.my/3250/1/1299.pdf |