Low power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logic
In this paper we have analyzed an 8-bit multiplier circuit using non clocked pass gate families with help of carry save multiplier (CSA) technique. The multiplier cell of the adder is designed by using pass transistors (n-transistors), p-transistors used as cross-coupled devices. The adder cell is d...
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| Format: | Conference or Workshop Item |
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2007
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| Online Access: | http://shdl.mmu.edu.my/3161/ |
| _version_ | 1848790250723213312 |
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| author | Senthilpari, C. Singh, Ajay Kumar Diwakar, K. |
| author_facet | Senthilpari, C. Singh, Ajay Kumar Diwakar, K. |
| author_sort | Senthilpari, C. |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | In this paper we have analyzed an 8-bit multiplier circuit using non clocked pass gate families with help of carry save multiplier (CSA) technique. The multiplier cell of the adder is designed by using pass transistors (n-transistors), p-transistors used as cross-coupled devices. The adder cell is designed by using multiplexing control input techniques. A combination of n- and p-transistors used on the mirror logic and inverters of full adder circuit. These multipliers are useful in the portable battery operated multimedia devices for energy efficient. The 8 bit multiplier circuit has been simulated using microwind3 VLSI layout CAD tool. We have analyzed the power dissipation, propagation delay, PDP and EPI (energy per instruction) and compared our results with other pass transistor logics as well as published results. From the simulated results it was found that the power dissipation and propagation delay are low in our designed non-clocked pass transistor logics. Our multiplier circuit shows a power dissipation improvement of 97.6% from Amir et.al and 46.30%, 23.24% and 0.15% from Rizwan et.al. Our multipliers gives better propagation delay compared to Rizwan et. al that are 89.56%, 88.39% and 88.31% |
| first_indexed | 2025-11-14T18:09:38Z |
| format | Conference or Workshop Item |
| id | mmu-3161 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:09:38Z |
| publishDate | 2007 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-31612011-10-18T06:07:56Z http://shdl.mmu.edu.my/3161/ Low power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logic Senthilpari, C. Singh, Ajay Kumar Diwakar, K. T Technology (General) QA75.5-76.95 Electronic computers. Computer science In this paper we have analyzed an 8-bit multiplier circuit using non clocked pass gate families with help of carry save multiplier (CSA) technique. The multiplier cell of the adder is designed by using pass transistors (n-transistors), p-transistors used as cross-coupled devices. The adder cell is designed by using multiplexing control input techniques. A combination of n- and p-transistors used on the mirror logic and inverters of full adder circuit. These multipliers are useful in the portable battery operated multimedia devices for energy efficient. The 8 bit multiplier circuit has been simulated using microwind3 VLSI layout CAD tool. We have analyzed the power dissipation, propagation delay, PDP and EPI (energy per instruction) and compared our results with other pass transistor logics as well as published results. From the simulated results it was found that the power dissipation and propagation delay are low in our designed non-clocked pass transistor logics. Our multiplier circuit shows a power dissipation improvement of 97.6% from Amir et.al and 46.30%, 23.24% and 0.15% from Rizwan et.al. Our multipliers gives better propagation delay compared to Rizwan et. al that are 89.56%, 88.39% and 88.31% 2007-11 Conference or Workshop Item NonPeerReviewed Senthilpari, C. and Singh, Ajay Kumar and Diwakar, K. (2007) Low power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logic. In: International Conference on Intelligent and Advanced Systems, 25-28 NOV 2007 , Kuala Lumpur, MALAYSIA. http://apps.webofknowledge.com/full_record.do?product=WOS&search_mode=GeneralSearch&qid=1&SID=S1iF85GI68kD2C5e51I&page=118&doc=1176 |
| spellingShingle | T Technology (General) QA75.5-76.95 Electronic computers. Computer science Senthilpari, C. Singh, Ajay Kumar Diwakar, K. Low power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logic |
| title | Low power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logic |
| title_full | Low power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logic |
| title_fullStr | Low power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logic |
| title_full_unstemmed | Low power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logic |
| title_short | Low power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logic |
| title_sort | low power and high speed 8x8 bit multiplier using non-clocked pass transistor logic |
| topic | T Technology (General) QA75.5-76.95 Electronic computers. Computer science |
| url | http://shdl.mmu.edu.my/3161/ http://shdl.mmu.edu.my/3161/ |