An 8-Gb/s half-rate clock and data recovery circuit
This paper presents circuit design and simulation result of the 8-Gb/s half-rate clock and data recovery circuit (CDR) by 0.18u process technology. The linear phase detector was used for the CDR and able to give linear relation of the phase error between 35ps to 110ps. While the data output jitter p...
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| Format: | Conference or Workshop Item |
| Published: |
2007
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| Online Access: | http://shdl.mmu.edu.my/3153/ |
| _version_ | 1848790248549515264 |
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| author | Khalek, Faizal Sulaiman, Mohd-Shahiman Yusoff, Zubaida |
| author_facet | Khalek, Faizal Sulaiman, Mohd-Shahiman Yusoff, Zubaida |
| author_sort | Khalek, Faizal |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | This paper presents circuit design and simulation result of the 8-Gb/s half-rate clock and data recovery circuit (CDR) by 0.18u process technology. The linear phase detector was used for the CDR and able to give linear relation of the phase error between 35ps to 110ps. While the data output jitter p-p is 4.6ps and the clock jitter p-p is 6.6ps. The power consumption is 55mW from a 1.8V voltage supply. |
| first_indexed | 2025-11-14T18:09:36Z |
| format | Conference or Workshop Item |
| id | mmu-3153 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:09:36Z |
| publishDate | 2007 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-31532011-10-18T06:39:45Z http://shdl.mmu.edu.my/3153/ An 8-Gb/s half-rate clock and data recovery circuit Khalek, Faizal Sulaiman, Mohd-Shahiman Yusoff, Zubaida T Technology (General) QA75.5-76.95 Electronic computers. Computer science This paper presents circuit design and simulation result of the 8-Gb/s half-rate clock and data recovery circuit (CDR) by 0.18u process technology. The linear phase detector was used for the CDR and able to give linear relation of the phase error between 35ps to 110ps. While the data output jitter p-p is 4.6ps and the clock jitter p-p is 6.6ps. The power consumption is 55mW from a 1.8V voltage supply. 2007-12 Conference or Workshop Item NonPeerReviewed Khalek, Faizal and Sulaiman, Mohd-Shahiman and Yusoff, Zubaida (2007) An 8-Gb/s half-rate clock and data recovery circuit. In: IEEE International Conference on Electron Devices and Solid-State Circuits, 20-22 DEC 2007 , Tainan, TAIWAN. http://apps.webofknowledge.com/full_record.do?product=WOS&search_mode=GeneralSearch&qid=1&SID=S1iF85GI68kD2C5e51I&page=117&doc=1170 |
| spellingShingle | T Technology (General) QA75.5-76.95 Electronic computers. Computer science Khalek, Faizal Sulaiman, Mohd-Shahiman Yusoff, Zubaida An 8-Gb/s half-rate clock and data recovery circuit |
| title | An 8-Gb/s half-rate clock and data recovery circuit |
| title_full | An 8-Gb/s half-rate clock and data recovery circuit |
| title_fullStr | An 8-Gb/s half-rate clock and data recovery circuit |
| title_full_unstemmed | An 8-Gb/s half-rate clock and data recovery circuit |
| title_short | An 8-Gb/s half-rate clock and data recovery circuit |
| title_sort | 8-gb/s half-rate clock and data recovery circuit |
| topic | T Technology (General) QA75.5-76.95 Electronic computers. Computer science |
| url | http://shdl.mmu.edu.my/3153/ http://shdl.mmu.edu.my/3153/ |