An 8-Gb/s half-rate clock and data recovery circuit
This paper presents circuit design and simulation result of the 8-Gb/s half-rate clock and data recovery circuit (CDR) by 0.18u process technology. The linear phase detector was used for the CDR and able to give linear relation of the phase error between 35ps to 110ps. While the data output jitter p...
| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Published: |
2007
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| Subjects: | |
| Online Access: | http://shdl.mmu.edu.my/3153/ |