Low-power dual-port asynchronous CMOS SRAM design techniques

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Low-power dual-port asynchronous CMOS SRAM design techniques

This paper describes the review and short tutorial on design techniques for low-power SRAM, focusing on the design of a 1-Mb CMOS SRAM on CMOS 0.25-mu m process. The building blocks of the SRAM are individually discussed and various techniques are described, with the most appropriate one chosen for...

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Bibliographic Details
Main Authors:	Tan, Soon-Hwei, Loh, Poh-Yee, Sulaiman, Mohd-Shahiman, Yusoff, Zubaida
Format:	Article
Published:	SOC MICROELECTRONICS 2007
Subjects:	T Technology (General) QA75.5-76.95 Electronic computers. Computer science
Online Access:	http://shdl.mmu.edu.my/3052/

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