Low-power dual-port asynchronous CMOS SRAM design techniques
This paper describes the review and short tutorial on design techniques for low-power SRAM, focusing on the design of a 1-Mb CMOS SRAM on CMOS 0.25-mu m process. The building blocks of the SRAM are individually discussed and various techniques are described, with the most appropriate one chosen for...
| Main Authors: | , , , |
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| Format: | Article |
| Published: |
SOC MICROELECTRONICS
2007
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| Subjects: | |
| Online Access: | http://shdl.mmu.edu.my/3052/ |