| Summary: | This paper examines the performance of two 128-bit ROM circuits, implemented on Silterra 0.18u CMOS process. The first circuit is built using standard NMOS transistors, runs on 0.9V supply voltage, has gate voltage of 0.45V and consumes 102.07 mu W power. The second circuit is designed partly using Dynamic Threshold-Voltage MOSFET (DTMOS) transistors with the aim to minimize power consumption. It runs on 0.7V supply and has gate voltage of 0.35V. The DTMOS approach is implemented on the 128-bit ROM core and in the pull up circuit of the column decoder. The latter ROM circuit's power consumption is 38.93 mu W, 61.86% less than the former, at the expenses of larger die area due to the usage of deep n-well process. The standard and DTMOST circuits have the die areas of 0.139 mu m2 and 0.235 mu m2, respectively.
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