Low power ROM Employing Dynamic Threshold-Voltage MOSFET (DTMOS) Technique
This paper examines the performance of two 128-bit ROM circuits, implemented on Silterra 0.18u CMOS process. The first circuit is built using standard NMOS transistors, runs on 0.9V supply voltage, has gate voltage of 0.45V and consumes 102.07 mu W power. The second circuit is designed partly using...
| Main Authors: | , , , , |
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| Format: | Conference or Workshop Item |
| Published: |
2008
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| Subjects: | |
| Online Access: | http://shdl.mmu.edu.my/2890/ |