A 5Gbit/s CMOS clock and data recovery circuit
This paper presents a half-rate 5Gb/s clock and data recovery circuit. Retiming of data is done by the linear PD that provides practically no systematic offset for the frequency band of interest The circuit was designed in a 0.18-mu m CMOS process and occupies an active area of 0.2 x 0.32 mm(2). The...
| Main Authors: | , , , , |
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| Format: | Article |
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2005
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| Online Access: | http://shdl.mmu.edu.my/2407/ |
| _version_ | 1848790047541690368 |
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| author | Sulaiman , Mohd Shahiman Mohd-Yasin,, F Reaz,, Mamun B. I. Soon-Hwei,, Tan Kok-Siang,, Tan |
| author_facet | Sulaiman , Mohd Shahiman Mohd-Yasin,, F Reaz,, Mamun B. I. Soon-Hwei,, Tan Kok-Siang,, Tan |
| author_sort | Sulaiman , Mohd Shahiman |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | This paper presents a half-rate 5Gb/s clock and data recovery circuit. Retiming of data is done by the linear PD that provides practically no systematic offset for the frequency band of interest The circuit was designed in a 0.18-mu m CMOS process and occupies an active area of 0.2 x 0.32 mm(2). The CDR exhibits an RMS jitter of +/- 1.2 ps and a peak-to-peak jitter of 5ps. The power dissipation is 97mW from a 1.8-V supply. |
| first_indexed | 2025-11-14T18:06:24Z |
| format | Article |
| id | mmu-2407 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:06:24Z |
| publishDate | 2005 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-24072011-08-22T03:01:20Z http://shdl.mmu.edu.my/2407/ A 5Gbit/s CMOS clock and data recovery circuit Sulaiman , Mohd Shahiman Mohd-Yasin,, F Reaz,, Mamun B. I. Soon-Hwei,, Tan Kok-Siang,, Tan TA Engineering (General). Civil engineering (General) This paper presents a half-rate 5Gb/s clock and data recovery circuit. Retiming of data is done by the linear PD that provides practically no systematic offset for the frequency band of interest The circuit was designed in a 0.18-mu m CMOS process and occupies an active area of 0.2 x 0.32 mm(2). The CDR exhibits an RMS jitter of +/- 1.2 ps and a peak-to-peak jitter of 5ps. The power dissipation is 97mW from a 1.8-V supply. 2005 Article NonPeerReviewed Sulaiman , Mohd Shahiman and Mohd-Yasin,, F and Reaz,, Mamun B. I. and Soon-Hwei,, Tan and Kok-Siang,, Tan (2005) A 5Gbit/s CMOS clock and data recovery circuit. 2005 IEEE CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, PROCEEDINGS. pp. 415-418. |
| spellingShingle | TA Engineering (General). Civil engineering (General) Sulaiman , Mohd Shahiman Mohd-Yasin,, F Reaz,, Mamun B. I. Soon-Hwei,, Tan Kok-Siang,, Tan A 5Gbit/s CMOS clock and data recovery circuit |
| title | A 5Gbit/s CMOS clock and data recovery circuit |
| title_full | A 5Gbit/s CMOS clock and data recovery circuit |
| title_fullStr | A 5Gbit/s CMOS clock and data recovery circuit |
| title_full_unstemmed | A 5Gbit/s CMOS clock and data recovery circuit |
| title_short | A 5Gbit/s CMOS clock and data recovery circuit |
| title_sort | 5gbit/s cmos clock and data recovery circuit |
| topic | TA Engineering (General). Civil engineering (General) |
| url | http://shdl.mmu.edu.my/2407/ |