Power Deduction in Digital Signal Processing Circuit using Inventive CPL Subtractor Circuit
The proposed 4 bit subtractor circuit is designed by using bit slice method of complementary pass transistor logic (CPL), which is suitable for applications like fast shifting; multiplier/adder in the loop cycle of DSP data processing device. The circuit can perform real time computational tasks at...
| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Published: |
2006
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| Subjects: | |
| Online Access: | http://shdl.mmu.edu.my/2055/ |