Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families

QR Code

Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families

In the present paper we have designed a 16-bit adder circuits with basic pass transistor circuit approach and different topology for implementation. The proposed multiplexing control input techniques of the adder circuits are developed by the carry save adder (CSA) technique. The different logic cel...

Full description

Bibliographic Details
Main Authors:	Senthilpari, Chinnaiyan, Singh, Ajay Kumar, Arokiasamy, A.
Format:	Conference or Workshop Item
Language:	English
Published:	IEEE 2007
Subjects:	TA Engineering (General). Civil engineering (General)
Online Access:	http://shdl.mmu.edu.my/2043/ http://shdl.mmu.edu.my/2043/1/Statistical%20analysis%20of%20power%20delay%20estimation%20in%20adder%20circuit.pdf

Similar Items

Low power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logic
by: Senthilpari, C., et al.
Published: (2007)

Full adder circuit design with novel lower complexity XOR gate in QCA technology
by: H. Majeed, Ali, et al.
Published: (2020)

Clock Gating Assertion Check An Approach Towards Efficient Verification Closure On Clock Gating Functionality
by: Wang, Jian Zhong
Published: (2017)

Implementation and self-checking of different adder circuits
by: Hassan, Hasliza
Published: (2020)

Power Deduction in Digital Signal Processing Circuit using Inventive CPL Subtractor Circuit
by: Senthilpari, C., et al.
Published: (2006)

Clock Gating Technique For Power Reduction In Digital Design
by: Khor, Peng Lim
Published: (2012)

Circuit design of a clock data recovery
by: Ashari, Zainab, et al.
Published: (2011)

An analytical study of undoped symmetric double gate MOSFET (SDG)
by: Singh, Ajay Kumar
Published: (2011)

Reversible Logic Gate Implementation as Switch Controlled Reversible Full Adder/Subtractor
by: Gopal, Lenin, et al.
Published: (2014)

Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach
by: C., Senthilpari
Published: (2009)

A 5Gbit/s CMOS clock and data recovery circuit
by: Sulaiman , Mohd Shahiman, et al.
Published: (2005)

High speed adder
by: Dagrious, Jihob.
Published: (2009)

A low power multiplexer based pass transistor logic full adder
by: Kamsani, Noor Ain, et al.
Published: (2015)

Hardware modeling of binary coded decimal adder in field programmable gate array
by: Ibrahimy, Muhammad Ibn, et al.
Published: (2013)

Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell
by: SENTHILPARI, C, et al.
Published: (2008)

A methodology for optimum delay, skew, and power performances in an FPGA clock network
by: Sulaiman, Mohd S.
Published: (2006)

Fault Diagnosis On Vlsi Adder Circuits Using Artificial Neural Network
by: Pui , Min San
Published: (2015)

CMOS Low Power Analogue Adder
by: Tan, Yu Sheng
Published: (2020)

Comparison of parallel prefix adder (PPA)
by: Voon, Peter
Published: (2010)

High-Performance CMOS Clock And Data Recovery Circuit
by: Tan, Kok Siang
Published: (2006)

Design of high-speed clock and data recovery circuits
by: Tan, Kok Siang, et al.
Published: (2007)

VLSI implementation of full adder-subtractor design
by: Ahmad, Nabihah, et al.
Published: (2017)

A comparative study on the implementation of reversible Binary Coded Decimal (BCD) Adder performance on Field Programmable Gate array (FPGA)
by: Tham, N., et al.
Published: (2014)

Low power 130 nm CMOS Johnson Counter with clock gating technique
by: Amran, Nur Syuhadah, et al.
Published: (2018)

An 8-Gb/s half-rate clock and data recovery circuit
by: Khalek, Faizal, et al.
Published: (2007)

Chess digital clock
by: Rosmira, Roslan
Published: (2008)

CMOS technology for increasing efficiency of clock gating techniques using tri-state buffer
by: Mohammed, Maan Hameed, et al.
Published: (2017)

Low Power Design Of 8b/10b Encoder And 10b/8b Decoder Using Clock Gating Technique
by: Ong, Ji Xian
Published: (2017)

Development of solar digital clock
by: Mohd Hafeez, Mohd Nasir
Published: (2009)

A Monolithic 622MB/S Half Rate Clock And Data Recovery Circuit Utilizing A Novel Linear Phase Detector.
by: Chen, Hau Jiun, et al.
Published: (2004)

A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit
by: Tan, Kok Siang, et al.
Published: (2007)

Design and Analysis of a New Carbon Nanotube Full Adder Cell
by: Ghadiry, M. H., et al.
Published: (2011)

Design of low quantum cost reversible BCD adder
by: Cheng, C., et al.
Published: (2016)

Fast clock tree generation using exact zero skew clock routing algorithm
by: Reaz, Mamun Ibn, et al.
Published: (2009)

Highly stable Delta-Sigma Modulator for industrial applications
by: Diwakar, K., et al.
Published: (2008)

The clock is ticking
by: Zawawi, Dahlia, et al.
Published: (2009)

Zero skew clock routing for fast clock tree generation
by: Reaz, Mamun Ibn, et al.
Published: (2008)

Bridging clock gaps in Mega-Constellation LEO satellites
by: Wang, Kan, et al.
Published: (2022)

LEO satellite clock analysis and prediction for positioning applications
by: Wang, Kan, et al.
Published: (2021)

Hybrid HVDC circuit breaker with self-powered gate drives
by: Effah, Francis Boafo, et al.
Published: (2016)