Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families
In the present paper we have designed a 16-bit adder circuits with basic pass transistor circuit approach and different topology for implementation. The proposed multiplexing control input techniques of the adder circuits are developed by the carry save adder (CSA) technique. The different logic cel...
| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2007
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| Subjects: | |
| Online Access: | http://shdl.mmu.edu.my/2043/ http://shdl.mmu.edu.my/2043/1/Statistical%20analysis%20of%20power%20delay%20estimation%20in%20adder%20circuit.pdf |