Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families
In the present paper we have designed a 16-bit adder circuits with basic pass transistor circuit approach and different topology for implementation. The proposed multiplexing control input techniques of the adder circuits are developed by the carry save adder (CSA) technique. The different logic cel...
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| Format: | Conference or Workshop Item |
| Language: | English |
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IEEE
2007
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| Online Access: | http://shdl.mmu.edu.my/2043/ http://shdl.mmu.edu.my/2043/1/Statistical%20analysis%20of%20power%20delay%20estimation%20in%20adder%20circuit.pdf |
| _version_ | 1848789948633710592 |
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| author | Senthilpari, Chinnaiyan Singh, Ajay Kumar Arokiasamy, A. |
| author_facet | Senthilpari, Chinnaiyan Singh, Ajay Kumar Arokiasamy, A. |
| author_sort | Senthilpari, Chinnaiyan |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | In the present paper we have designed a 16-bit adder circuits with basic pass transistor circuit approach and different topology for implementation. The proposed multiplexing control input techniques of the adder circuits are developed by the carry save adder (CSA) technique. The different logic cells, used for various pass gates circuit design styles are evaluated in terms of area, propagation delay, power dissipation and propagation delay product. The design styles are compared by performing detailed transistor-level simulations on a benchmark circuit (CSA adder) using DSCH3 and Microwind3. We have analysed the results in a statistical way. We have compared our results with the various published results of adder circuits Me found that the speed of the our proposed circuit is enhanced and power consumption as well as the area has reduced tremendously due to multiplexing control input technique. Comparing the simulated results with other pass logic designs, it was observed that in all existing logic CPL is a promising candidate for future logic design. |
| first_indexed | 2025-11-14T18:04:50Z |
| format | Conference or Workshop Item |
| id | mmu-2043 |
| institution | Multimedia University |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-14T18:04:50Z |
| publishDate | 2007 |
| publisher | IEEE |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-20432021-04-22T16:26:41Z http://shdl.mmu.edu.my/2043/ Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families Senthilpari, Chinnaiyan Singh, Ajay Kumar Arokiasamy, A. TA Engineering (General). Civil engineering (General) In the present paper we have designed a 16-bit adder circuits with basic pass transistor circuit approach and different topology for implementation. The proposed multiplexing control input techniques of the adder circuits are developed by the carry save adder (CSA) technique. The different logic cells, used for various pass gates circuit design styles are evaluated in terms of area, propagation delay, power dissipation and propagation delay product. The design styles are compared by performing detailed transistor-level simulations on a benchmark circuit (CSA adder) using DSCH3 and Microwind3. We have analysed the results in a statistical way. We have compared our results with the various published results of adder circuits Me found that the speed of the our proposed circuit is enhanced and power consumption as well as the area has reduced tremendously due to multiplexing control input technique. Comparing the simulated results with other pass logic designs, it was observed that in all existing logic CPL is a promising candidate for future logic design. IEEE 2007 Conference or Workshop Item NonPeerReviewed text en http://shdl.mmu.edu.my/2043/1/Statistical%20analysis%20of%20power%20delay%20estimation%20in%20adder%20circuit.pdf Senthilpari, Chinnaiyan and Singh, Ajay Kumar and Arokiasamy, A. (2007) Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families. In: 2006 International Conference on Electrical and Computer Engineering, 19-21 Dec. 2006, Dhaka, Bangladesh. https://ieeexplore.ieee.org/document/4178516 10.1109/ICECE.2006.355680 10.1109/ICECE.2006.355680 10.1109/ICECE.2006.355680 |
| spellingShingle | TA Engineering (General). Civil engineering (General) Senthilpari, Chinnaiyan Singh, Ajay Kumar Arokiasamy, A. Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families |
| title | Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families |
| title_full | Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families |
| title_fullStr | Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families |
| title_full_unstemmed | Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families |
| title_short | Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families |
| title_sort | statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families |
| topic | TA Engineering (General). Civil engineering (General) |
| url | http://shdl.mmu.edu.my/2043/ http://shdl.mmu.edu.my/2043/ http://shdl.mmu.edu.my/2043/ http://shdl.mmu.edu.my/2043/1/Statistical%20analysis%20of%20power%20delay%20estimation%20in%20adder%20circuit.pdf |