APA (7th ed.) Citation

Senthilpari, C., Singh, A. K., & Arokiasamy, A. (2007). Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families. IEEE.

Chicago Style (17th ed.) Citation

Senthilpari, Chinnaiyan, Ajay Kumar Singh, and A. Arokiasamy. Statistical Analysis of Power Delay Estimation in Adder Circuit Using Non-clocked Pass Gate Families. IEEE, 2007.

MLA (9th ed.) Citation

Senthilpari, Chinnaiyan, et al. Statistical Analysis of Power Delay Estimation in Adder Circuit Using Non-clocked Pass Gate Families. IEEE, 2007.