A methodology for optimum delay, skew, and power performances in an FPGA clock network
A methodology for FPGA clock network optimisation is presented. The algorithms for optimisation of clock skew, delay, and power considering slew rate constraint for an FPGA fixed-clock network are implemented and verified on SX 32 FPGA chip. Measurements indicated a 60% reduction in clock slew rate...
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| Format: | Article |
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2006
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| Online Access: | http://shdl.mmu.edu.my/1966/ |
| _version_ | 1848789926677577728 |
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| author | Sulaiman, Mohd S. |
| author_facet | Sulaiman, Mohd S. |
| author_sort | Sulaiman, Mohd S. |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | A methodology for FPGA clock network optimisation is presented. The algorithms for optimisation of clock skew, delay, and power considering slew rate constraint for an FPGA fixed-clock network are implemented and verified on SX 32 FPGA chip. Measurements indicated a 60% reduction in clock slew rate and a 22% improvement in power dissipation when compared to the results of the initial, un-optimised chip. |
| first_indexed | 2025-11-14T18:04:29Z |
| format | Article |
| id | mmu-1966 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:04:29Z |
| publishDate | 2006 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-19662011-09-23T03:21:08Z http://shdl.mmu.edu.my/1966/ A methodology for optimum delay, skew, and power performances in an FPGA clock network Sulaiman, Mohd S. TA Engineering (General). Civil engineering (General) A methodology for FPGA clock network optimisation is presented. The algorithms for optimisation of clock skew, delay, and power considering slew rate constraint for an FPGA fixed-clock network are implemented and verified on SX 32 FPGA chip. Measurements indicated a 60% reduction in clock slew rate and a 22% improvement in power dissipation when compared to the results of the initial, un-optimised chip. 2006-06 Article NonPeerReviewed Sulaiman, Mohd S. (2006) A methodology for optimum delay, skew, and power performances in an FPGA clock network. INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS, 36 (2). pp. 85-90. ISSN 0352-9045 http://apps.webofknowledge.com |
| spellingShingle | TA Engineering (General). Civil engineering (General) Sulaiman, Mohd S. A methodology for optimum delay, skew, and power performances in an FPGA clock network |
| title | A methodology for optimum delay, skew, and power performances in an FPGA clock network |
| title_full | A methodology for optimum delay, skew, and power performances in an FPGA clock network |
| title_fullStr | A methodology for optimum delay, skew, and power performances in an FPGA clock network |
| title_full_unstemmed | A methodology for optimum delay, skew, and power performances in an FPGA clock network |
| title_short | A methodology for optimum delay, skew, and power performances in an FPGA clock network |
| title_sort | methodology for optimum delay, skew, and power performances in an fpga clock network |
| topic | TA Engineering (General). Civil engineering (General) |
| url | http://shdl.mmu.edu.my/1966/ http://shdl.mmu.edu.my/1966/ |