A methodology for optimum delay, skew, and power performances in an FPGA clock network
A methodology for FPGA clock network optimisation is presented. The algorithms for optimisation of clock skew, delay, and power considering slew rate constraint for an FPGA fixed-clock network are implemented and verified on SX 32 FPGA chip. Measurements indicated a 60% reduction in clock slew rate...
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| Format: | Article |
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2006
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| Online Access: | http://shdl.mmu.edu.my/1966/ |