Sulaiman, M. S. (2006). A methodology for optimum delay, skew, and power performances in an FPGA clock network.
Chicago Style (17th ed.) CitationSulaiman, Mohd S. A Methodology for Optimum Delay, Skew, and Power Performances in an FPGA Clock Network. 2006.
MLA (9th ed.) CitationSulaiman, Mohd S. A Methodology for Optimum Delay, Skew, and Power Performances in an FPGA Clock Network. 2006.
Warning: These citations may not always be 100% accurate.