A 1.3-Gsample/s interpolation with flash CMOS ADC based on active interpolation technique
In this paper, the design of a high-speed low-voltage CMOS interpolation with flash analog-to-digital converter (ADC) in CMOS 0.18-mu m process is presented. The use of summing differential amplifiers operating in continuous time for interpolation and resistor averaging circuit have significantly im...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
2006
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| Subjects: | |
| Online Access: | http://shdl.mmu.edu.my/1959/ http://shdl.mmu.edu.my/1959/1/1315.pdf |