A study and design of CMOS H-Tree clock distribution network in system-on-chip
A design of a low skew clock distribution network is presented based on the TSMC 0.18 mu m CMOS technology. This work first investigated various aspects in designing a clock distribution network. After that, the design methodology for the chosen H-Tree clock network topology is presented. A series o...
| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
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2009
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| Online Access: | http://shdl.mmu.edu.my/1922/ |
| _version_ | 1848789914759462912 |
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| author | Loo, Wei-Khee Tan, Kok-Siang Teh, Ying-Khai |
| author_facet | Loo, Wei-Khee Tan, Kok-Siang Teh, Ying-Khai |
| author_sort | Loo, Wei-Khee |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | A design of a low skew clock distribution network is presented based on the TSMC 0.18 mu m CMOS technology. This work first investigated various aspects in designing a clock distribution network. After that, the design methodology for the chosen H-Tree clock network topology is presented. A series of design performance analyses such as clock delay, skew, rise and fall time, supply voltage and temperature variations and power consumption were compared for both pre-layout and post-layout simulation results. Pre-layout and post-layout simulation results validated the 3-segment pi-model. The clock network designed is able to operate up to maximum clock speed of 1.1GHz for a 1 x 1 mm(2) chip with zero skew. |
| first_indexed | 2025-11-14T18:04:18Z |
| format | Conference or Workshop Item |
| id | mmu-1922 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:04:18Z |
| publishDate | 2009 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-19222011-09-23T03:18:00Z http://shdl.mmu.edu.my/1922/ A study and design of CMOS H-Tree clock distribution network in system-on-chip Loo, Wei-Khee Tan, Kok-Siang Teh, Ying-Khai T Technology (General) QA75.5-76.95 Electronic computers. Computer science A design of a low skew clock distribution network is presented based on the TSMC 0.18 mu m CMOS technology. This work first investigated various aspects in designing a clock distribution network. After that, the design methodology for the chosen H-Tree clock network topology is presented. A series of design performance analyses such as clock delay, skew, rise and fall time, supply voltage and temperature variations and power consumption were compared for both pre-layout and post-layout simulation results. Pre-layout and post-layout simulation results validated the 3-segment pi-model. The clock network designed is able to operate up to maximum clock speed of 1.1GHz for a 1 x 1 mm(2) chip with zero skew. 2009-10 Conference or Workshop Item NonPeerReviewed Loo, Wei-Khee and Tan, Kok-Siang and Teh, Ying-Khai (2009) A study and design of CMOS H-Tree clock distribution network in system-on-chip. In: IEEE 8th International Conference on ASIC Location: Changsha, PEOPLES R CHINA, OCT 20-23, 2009 , IEEE Beijing Sect; Fudan Univ; IEEE China Council; Natl Univ Def Tech; IEEE CAS, IEEE SSCS; Chinese Inst Elect. http://dx.doi.org/10.1109/ASICON.2009.5351254 doi:10.1109/ASICON.2009.5351254 doi:10.1109/ASICON.2009.5351254 |
| spellingShingle | T Technology (General) QA75.5-76.95 Electronic computers. Computer science Loo, Wei-Khee Tan, Kok-Siang Teh, Ying-Khai A study and design of CMOS H-Tree clock distribution network in system-on-chip |
| title | A study and design of CMOS H-Tree clock distribution network in system-on-chip |
| title_full | A study and design of CMOS H-Tree clock distribution network in system-on-chip |
| title_fullStr | A study and design of CMOS H-Tree clock distribution network in system-on-chip |
| title_full_unstemmed | A study and design of CMOS H-Tree clock distribution network in system-on-chip |
| title_short | A study and design of CMOS H-Tree clock distribution network in system-on-chip |
| title_sort | study and design of cmos h-tree clock distribution network in system-on-chip |
| topic | T Technology (General) QA75.5-76.95 Electronic computers. Computer science |
| url | http://shdl.mmu.edu.my/1922/ http://shdl.mmu.edu.my/1922/ http://shdl.mmu.edu.my/1922/ |