High-Performance CMOS Clock And Data Recovery Circuit
In this dissertation, the design of a 5Gb/s CDR circuit in Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.18 -1.8V standard CMOS process based on a linear half-rate linear architecture is presented. Half-rate architecture allows a voltage controlled oscillator (VCO) to run at one-half of it...
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| Format: | Thesis |
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2006
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| Online Access: | http://shdl.mmu.edu.my/1094/ |
| _version_ | 1848789691092959232 |
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| author | Tan, Kok Siang |
| author_facet | Tan, Kok Siang |
| author_sort | Tan, Kok Siang |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | In this dissertation, the design of a 5Gb/s CDR circuit in Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.18 -1.8V standard CMOS process based on a linear half-rate linear architecture is presented. Half-rate architecture allows a voltage controlled oscillator (VCO) to run at one-half of its input data rate by utilizing both rising and falling edges of VCO output to sample jittery non-return zero (NRZ) data. Having a VCO running at one-half of data rate significantly reduces total jitter and power consumption. |
| first_indexed | 2025-11-14T18:00:44Z |
| format | Thesis |
| id | mmu-1094 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:00:44Z |
| publishDate | 2006 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-10942010-08-05T03:38:43Z http://shdl.mmu.edu.my/1094/ High-Performance CMOS Clock And Data Recovery Circuit Tan, Kok Siang QA76.75-76.765 Computer software In this dissertation, the design of a 5Gb/s CDR circuit in Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.18 -1.8V standard CMOS process based on a linear half-rate linear architecture is presented. Half-rate architecture allows a voltage controlled oscillator (VCO) to run at one-half of its input data rate by utilizing both rising and falling edges of VCO output to sample jittery non-return zero (NRZ) data. Having a VCO running at one-half of data rate significantly reduces total jitter and power consumption. 2006-09 Thesis NonPeerReviewed Tan, Kok Siang (2006) High-Performance CMOS Clock And Data Recovery Circuit. Masters thesis, Multimedia University. http://myto.perpun.net.my/metoalogin/logina.php |
| spellingShingle | QA76.75-76.765 Computer software Tan, Kok Siang High-Performance CMOS Clock And Data Recovery Circuit |
| title | High-Performance CMOS Clock And Data Recovery Circuit |
| title_full | High-Performance CMOS Clock And Data Recovery Circuit |
| title_fullStr | High-Performance CMOS Clock And Data Recovery Circuit |
| title_full_unstemmed | High-Performance CMOS Clock And Data Recovery Circuit |
| title_short | High-Performance CMOS Clock And Data Recovery Circuit |
| title_sort | high-performance cmos clock and data recovery circuit |
| topic | QA76.75-76.765 Computer software |
| url | http://shdl.mmu.edu.my/1094/ http://shdl.mmu.edu.my/1094/ |