A comparative study on the implementation of reversible Binary Coded Decimal (BCD) Adder performance on Field Programmable Gate array (FPGA)

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A comparative study on the implementation of reversible Binary Coded Decimal (BCD) Adder performance on Field Programmable Gate array (FPGA)

In this paper, we present a performance comparison of Binary Coded Decimal (BCD) Adders on Field Programmable Gate Logic (FPGA) for functional and behavioural verification. Although it does not prove that the circuit is reversible, implementation on FPGA serves as a platform for functional verificat...

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Bibliographic Details
Main Authors:	Tham, N., Gopalaiy, A., Gopal, Lenin, Singh, A.
Format:	Conference Paper
Published:	Institute of Electrical and Electronics Engineers Inc. 2014
Online Access:	http://hdl.handle.net/20.500.11937/29437

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