Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)
An error tolerant hardware efficient very large scale integration (VLSI) architecture for bit parallel systolic multiplication over dual base, which can be pipelined, is presented. Since this architecture has the features of regularity, modularity and unidirectional data flow, this structure is well...
| Main Authors: | Singh, Ashutosh Kumar, Bera, A., Rahaman, H., Mathew, J., Pradhan, D. |
|---|---|
| Format: | Journal Article |
| Published: |
University of Electronic Science and Technology
2009
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| Subjects: | |
| Online Access: | http://hdl.handle.net/20.500.11937/20443 |
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