Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)

Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)

An error tolerant hardware efficient very large scale integration (VLSI) architecture for bit parallel systolic multiplication over dual base, which can be pipelined, is presented. Since this architecture has the features of regularity, modularity and unidirectional data flow, this structure is well...

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Bibliographic Details
Main Authors: Singh, Ashutosh Kumar, Bera, A., Rahaman, H., Mathew, J., Pradhan, D.
Format: Journal Article
Published: University of Electronic Science and Technology 2009
Subjects:
Reed-Solomon (RS) codes
error correction
finite field
Bit parallel
systolic
very large scale integration (VLSI) testing
Online Access:http://hdl.handle.net/20.500.11937/20443

Internet

http://hdl.handle.net/20.500.11937/20443

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