Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)
An error tolerant hardware efficient very large scale integration (VLSI) architecture for bit parallel systolic multiplication over dual base, which can be pipelined, is presented. Since this architecture has the features of regularity, modularity and unidirectional data flow, this structure is well...
| Main Authors: | , , , , |
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| Format: | Journal Article |
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University of Electronic Science and Technology
2009
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| Online Access: | http://hdl.handle.net/20.500.11937/20443 |
| _version_ | 1848750306387558400 |
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| author | Singh, Ashutosh Kumar Bera, A. Rahaman, H. Mathew, J. Pradhan, D. |
| author_facet | Singh, Ashutosh Kumar Bera, A. Rahaman, H. Mathew, J. Pradhan, D. |
| author_sort | Singh, Ashutosh Kumar |
| building | Curtin Institutional Repository |
| collection | Online Access |
| description | An error tolerant hardware efficient very large scale integration (VLSI) architecture for bit parallel systolic multiplication over dual base, which can be pipelined, is presented. Since this architecture has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. The architecture is implemented using Austria Micro System's 0.35 m CMOS (complementary metal oxide semiconductor) technology. This architecture can also operate over both the dual-base and polynomial base. |
| first_indexed | 2025-11-14T07:34:44Z |
| format | Journal Article |
| id | curtin-20.500.11937-20443 |
| institution | Curtin University Malaysia |
| institution_category | Local University |
| last_indexed | 2025-11-14T07:34:44Z |
| publishDate | 2009 |
| publisher | University of Electronic Science and Technology |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | curtin-20.500.11937-204432018-09-07T01:31:57Z Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) Singh, Ashutosh Kumar Bera, A. Rahaman, H. Mathew, J. Pradhan, D. Reed-Solomon (RS) codes error correction finite field Bit parallel systolic very large scale integration (VLSI) testing An error tolerant hardware efficient very large scale integration (VLSI) architecture for bit parallel systolic multiplication over dual base, which can be pipelined, is presented. Since this architecture has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. The architecture is implemented using Austria Micro System's 0.35 m CMOS (complementary metal oxide semiconductor) technology. This architecture can also operate over both the dual-base and polynomial base. 2009 Journal Article http://hdl.handle.net/20.500.11937/20443 University of Electronic Science and Technology fulltext |
| spellingShingle | Reed-Solomon (RS) codes error correction finite field Bit parallel systolic very large scale integration (VLSI) testing Singh, Ashutosh Kumar Bera, A. Rahaman, H. Mathew, J. Pradhan, D. Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) |
| title | Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) |
| title_full | Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) |
| title_fullStr | Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) |
| title_full_unstemmed | Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) |
| title_short | Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) |
| title_sort | error detecting dual basis bit parallel systolic multiplication architecture over gf(2m) |
| topic | Reed-Solomon (RS) codes error correction finite field Bit parallel systolic very large scale integration (VLSI) testing |
| url | http://hdl.handle.net/20.500.11937/20443 |