APA (7th ed.) Citation

Singh, A. K., Bera, A., Rahaman, H., Mathew, J., & Pradhan, D. (2009). Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m). University of Electronic Science and Technology.

Chicago Style (17th ed.) Citation

Singh, Ashutosh Kumar, A. Bera, H. Rahaman, J. Mathew, and D. Pradhan. Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m). University of Electronic Science and Technology, 2009.

MLA (9th ed.) Citation

Singh, Ashutosh Kumar, et al. Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m). University of Electronic Science and Technology, 2009.