A Galois field-based logic synthesis with testability
In deep-submicron very-large-scale integration (VLSI) systems, efficient circuit testability is one of the most demanding requirements. An automatic synthesis technique for designing efficiently testable logic circuits is one of the ways to tackle the problem. To this end, this study introduces the...
| Main Authors: | , , , , |
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| Format: | Journal Article |
| Published: |
IET
2010
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| Online Access: | http://hdl.handle.net/20.500.11937/15573 |
| _version_ | 1848748930128412672 |
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| author | Mathew, J. Jabir, A.M. Singh, Ashutosh Kumar Rahaman, H. Pradhan, D.K. |
| author_facet | Mathew, J. Jabir, A.M. Singh, Ashutosh Kumar Rahaman, H. Pradhan, D.K. |
| author_sort | Mathew, J. |
| building | Curtin Institutional Repository |
| collection | Online Access |
| description | In deep-submicron very-large-scale integration (VLSI) systems, efficient circuit testability is one of the most demanding requirements. An automatic synthesis technique for designing efficiently testable logic circuits is one of the ways to tackle the problem. To this end, this study introduces the generalised theory and a new fast efficient graph-based decomposition technique for the functions over finite fields defined over the set GF(N), where N is a power of a prime number, which utilises the data structure of the multiple-output decision diagrams. In particular, the proposed technique can decompose any N valued arbitrary function over the fields conjunctively and disjunctively. The proposed technique is capable of generating testable circuits. The experimental results show that the proposed method is more economical in terms of literal count compared to the existing approaches. Furthermore, the authors have shown that the basic block can be tested with only eight test vectors. |
| first_indexed | 2025-11-14T07:12:52Z |
| format | Journal Article |
| id | curtin-20.500.11937-15573 |
| institution | Curtin University Malaysia |
| institution_category | Local University |
| last_indexed | 2025-11-14T07:12:52Z |
| publishDate | 2010 |
| publisher | IET |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | curtin-20.500.11937-155732017-10-02T02:28:21Z A Galois field-based logic synthesis with testability Mathew, J. Jabir, A.M. Singh, Ashutosh Kumar Rahaman, H. Pradhan, D.K. In deep-submicron very-large-scale integration (VLSI) systems, efficient circuit testability is one of the most demanding requirements. An automatic synthesis technique for designing efficiently testable logic circuits is one of the ways to tackle the problem. To this end, this study introduces the generalised theory and a new fast efficient graph-based decomposition technique for the functions over finite fields defined over the set GF(N), where N is a power of a prime number, which utilises the data structure of the multiple-output decision diagrams. In particular, the proposed technique can decompose any N valued arbitrary function over the fields conjunctively and disjunctively. The proposed technique is capable of generating testable circuits. The experimental results show that the proposed method is more economical in terms of literal count compared to the existing approaches. Furthermore, the authors have shown that the basic block can be tested with only eight test vectors. 2010 Journal Article http://hdl.handle.net/20.500.11937/15573 10.1049/iet-cdt.2009.0055 IET restricted |
| spellingShingle | Mathew, J. Jabir, A.M. Singh, Ashutosh Kumar Rahaman, H. Pradhan, D.K. A Galois field-based logic synthesis with testability |
| title | A Galois field-based logic synthesis with testability |
| title_full | A Galois field-based logic synthesis with testability |
| title_fullStr | A Galois field-based logic synthesis with testability |
| title_full_unstemmed | A Galois field-based logic synthesis with testability |
| title_short | A Galois field-based logic synthesis with testability |
| title_sort | galois field-based logic synthesis with testability |
| url | http://hdl.handle.net/20.500.11937/15573 |