A Galois field-based logic synthesis with testability
In deep-submicron very-large-scale integration (VLSI) systems, efficient circuit testability is one of the most demanding requirements. An automatic synthesis technique for designing efficiently testable logic circuits is one of the ways to tackle the problem. To this end, this study introduces the...
| Main Authors: | , , , , |
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| Format: | Journal Article |
| Published: |
IET
2010
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| Online Access: | http://hdl.handle.net/20.500.11937/15573 |