Towards minimizing the risks of soft errors at the design level of embedded systems
The risks of soft errors increase with system complexity, reduction in operational voltages, exponential growth in transistors per chip, increases in clock frequencies and device shrinking. Research into techniques to cope with soft errors has mostly focused on post-design phases such as circuit lev...
| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
Curtin University
2009
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| Subjects: | |
| Online Access: | http://hdl.handle.net/20.500.11937/1300 |
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