A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and...

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Main Authors:	Abdulrazzaq, Bilal Isam, Abdul Halin, Izhal, Kawahito, Shoji, Mohd Sidek, Roslina, Shafie, Suhaidi, Md Yunus, Nurul Amziah
Format:	Article
Language:	English
Published:	SpringerOpen 2016
Online Access:	http://psasir.upm.edu.my/id/eprint/55978/ http://psasir.upm.edu.my/id/eprint/55978/ http://psasir.upm.edu.my/id/eprint/55978/ http://psasir.upm.edu.my/id/eprint/55978/1/55978.pdf

id	upm-55978
recordtype	eprints
spelling	upm-559782017-07-03T09:25:41Z http://psasir.upm.edu.my/id/eprint/55978/ A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance Abdulrazzaq, Bilal Isam Abdul Halin, Izhal Kawahito, Shoji Mohd Sidek, Roslina Shafie, Suhaidi Md Yunus, Nurul Amziah A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented. SpringerOpen 2016 Article PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/55978/1/55978.pdf Abdulrazzaq, Bilal Isam and Abdul Halin, Izhal and Kawahito, Shoji and Mohd Sidek, Roslina and Shafie, Suhaidi and Md Yunus, Nurul Amziah (2016) A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance. SpringerPlus, 5. art. no. 434. pp. 1-32. ISSN 2193-1801 https://springerplus.springeropen.com/articles/10.1186/s40064-016-2090-z 10.1186/s40064-016-2090-z
repository_type	Digital Repository
institution_category	Local University
institution	Universiti Putra Malaysia
building	UPM Institutional Repository
collection	Online Access
language	English
description	A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.
format	Article
author	Abdulrazzaq, Bilal Isam Abdul Halin, Izhal Kawahito, Shoji Mohd Sidek, Roslina Shafie, Suhaidi Md Yunus, Nurul Amziah
spellingShingle	Abdulrazzaq, Bilal Isam Abdul Halin, Izhal Kawahito, Shoji Mohd Sidek, Roslina Shafie, Suhaidi Md Yunus, Nurul Amziah A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance
author_facet	Abdulrazzaq, Bilal Isam Abdul Halin, Izhal Kawahito, Shoji Mohd Sidek, Roslina Shafie, Suhaidi Md Yunus, Nurul Amziah
author_sort	Abdulrazzaq, Bilal Isam
title	A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance
title_short	A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance
title_full	A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance
title_fullStr	A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance
title_full_unstemmed	A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance
title_sort	review on high-resolution cmos delay lines: towards sub-picosecond jitter performance
publisher	SpringerOpen
publishDate	2016
url	http://psasir.upm.edu.my/id/eprint/55978/ http://psasir.upm.edu.my/id/eprint/55978/ http://psasir.upm.edu.my/id/eprint/55978/ http://psasir.upm.edu.my/id/eprint/55978/1/55978.pdf
first_indexed	2018-09-07T18:41:02Z
last_indexed	2018-09-07T18:41:02Z
_version_	1610975189149941760

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

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