Valley-engineered ultra-thin silicon for high-performance junctionless transistors

Valley-engineered ultra-thin silicon for high-performance junctionless transistors

Extremely thin silicon show good mechanical flexibility because of their 2-D like structure and enhanced performance by the quantum confinement effect. In this paper, we demonstrate a junctionless FET which reveals a room temperature quantum confinement effect (RTQCE) achieved by a valley-engineerin...

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Main Authors: Kim, Seung-Yoon, Choi, Sung-Yool, Hwang, Wan Sik, Cho, Byung Jin
Format: Online
Language:English
Published: Nature Publishing Group 2016
Online Access:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4937383/
id pubmed-4937383
recordtype oai_dc
spelling pubmed-49373832016-07-13 Valley-engineered ultra-thin silicon for high-performance junctionless transistors Kim, Seung-Yoon Choi, Sung-Yool Hwang, Wan Sik Cho, Byung Jin Article Extremely thin silicon show good mechanical flexibility because of their 2-D like structure and enhanced performance by the quantum confinement effect. In this paper, we demonstrate a junctionless FET which reveals a room temperature quantum confinement effect (RTQCE) achieved by a valley-engineering of the silicon. The strain-induced band splitting and a quantum confinement effect induced from ultra-thin-body silicon are the two main mechanisms for valley engineering. These were obtained from the extremely well-controlled silicon surface roughness and high tensile strain in silicon, thereupon demonstrating a device mobility increase of ~500% in a 2.5 nm thick silicon channel device. Nature Publishing Group 2016-07-08 /pmc/articles/PMC4937383/ /pubmed/27389874 http://dx.doi.org/10.1038/srep29354 Text en Copyright © 2016, Macmillan Publishers Limited http://creativecommons.org/licenses/by/4.0/ This work is licensed under a Creative Commons Attribution 4.0 International License. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in the credit line; if the material is not included under the Creative Commons license, users will need to obtain permission from the license holder to reproduce the material. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/
repository_type Open Access Journal
institution_category Foreign Institution
institution US National Center for Biotechnology Information
building NCBI PubMed
collection Online Access
language English
format Online
author Kim, Seung-Yoon
Choi, Sung-Yool
Hwang, Wan Sik
Cho, Byung Jin
spellingShingle Kim, Seung-Yoon
Choi, Sung-Yool
Hwang, Wan Sik
Cho, Byung Jin
Valley-engineered ultra-thin silicon for high-performance junctionless transistors
author_facet Kim, Seung-Yoon
Choi, Sung-Yool
Hwang, Wan Sik
Cho, Byung Jin
author_sort Kim, Seung-Yoon
title Valley-engineered ultra-thin silicon for high-performance junctionless transistors
title_short Valley-engineered ultra-thin silicon for high-performance junctionless transistors
title_full Valley-engineered ultra-thin silicon for high-performance junctionless transistors
title_fullStr Valley-engineered ultra-thin silicon for high-performance junctionless transistors
title_full_unstemmed Valley-engineered ultra-thin silicon for high-performance junctionless transistors
title_sort valley-engineered ultra-thin silicon for high-performance junctionless transistors
description Extremely thin silicon show good mechanical flexibility because of their 2-D like structure and enhanced performance by the quantum confinement effect. In this paper, we demonstrate a junctionless FET which reveals a room temperature quantum confinement effect (RTQCE) achieved by a valley-engineering of the silicon. The strain-induced band splitting and a quantum confinement effect induced from ultra-thin-body silicon are the two main mechanisms for valley engineering. These were obtained from the extremely well-controlled silicon surface roughness and high tensile strain in silicon, thereupon demonstrating a device mobility increase of ~500% in a 2.5 nm thick silicon channel device.
publisher Nature Publishing Group
publishDate 2016
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4937383/
_version_ 1613605972292403200

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