Influence of HALO and source/drain implantation on threshold voltage in 45nm PMOS device

by Salehuddin, F., Ahmad, I., Hamid, F.A., Zaharim, A.
Published 2017

Effect of process parameter variations on threshold voltage in 45nm NMOS device

by Salehuddin, F., Ahmad, I., Hamid, F.A., Zaharim, A.
Published 2017

Impact of HALO structure on threshold voltage and leakage current in 45nm NMOS device

by Salehuddin, F., Ahmad, I., Hamid, F.A., Zaharim, A.
Published 2017

Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method

by Salehuddin, F., Ahmad, I., Hamid, F.A., Zaharim, A.
Published 2017

Characterization and optimizations of silicide thickness in 45nm pMOS device

by Salehuddin, F., Ahmad, I., Hamid, F.A., Zaharim, A.
Published 2017

Impact of different dose and angle in HALO structure for 45nm NMOS device

by Salehuddin, F., Ahmad, I., Hamid, F.A., Zaharim, A.
Published 2017

Optimization of process parameter variability in 45 nm PMOS device using Taguchi method

by Salehuddin, F., Ahmad, I., Hamid, F.A., Zaharim, A.
Published 2017

Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method

by Afifah Maheran, A.H., Menon, P.S., Ahmad, I., Salehuddin, F., Mohd Zain, A.S.
Published 2017

Application of taguchi method with the interaction test for lower DIBL IN WSix/TiO2 channel vertical double gate NMOS

by Kaharudin, K.E., Salehuddin, F., Zain, A.S.M., Aziz, M.N.I.A., Ahmad, I.
Published 2017

Optimization of process parameter variations on threshold voltage in Ultrathin Pillar Vertical Double Gate MOSFET Device

by Kaharudin, K.E., Hamidon, A.H., Salehuddin, F., Ifwat Abd Aziz, M.N., Ahmad, I.
Published 2017

Scaling down of the 32 nm to 22 nm gate length NMOS transistor

by Afifah Maheran, A.H., Menon, P.S., Ahmad, I., Elgomati, H.A., Majlis, B.Y., Salehuddin, F.
Published 2017

Cobalt silicide and titanium silicide effects on nano devices

by Elgomati, H.A., Majlis, B.Y., Salehuddin, F., Ahmad, I., Zaharim, A., Hamid, F.A.
Published 2017

Analyze of input process parameter variation on threshold voltage in 45nm n-channel MOSFET

by Salehuddin, F., Ahmad, I., Hamid, F.A., Zaharim, A., Elgomati, H.A., Majlis, B.Y.
Published 2017

Optimizing 35nm NMOS devices V TH and I LEAK by controlling active area and halo implantation dosage

by Elgomati, H.A., Majlis, B.Y., Salehuddin, F., Ahmad, I., Zaharim, A., Hamid, F.A.
Published 2017

Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device

by Salehuddin, F., Ahmad, I., Hamid, F.A., Zaharim, A., Hashim, U., Apte, P.R.
Published 2017

Taguchi modeling of process parameters in vdg-mosfet device for higher ION/IOFF ratio

by Kaharudin, K.E., Salehuddin, F., Hamidon, A.H., Aziz, M.N.I.A., Ahmad, I.
Published 2017

Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor

by Afifah Maheran, A.H., Menon, P.S., Ahmad, I., Shaari, S., Elgomati, H.A., Salehuddin, F.
Published 2017

Control factors optimization on threshold voltage and leakage current in 22 nm NMOS transistor using Taguchi method

by Afifah Maheran, A.H., Menon, P.S., Ahmad, I., Salehuddin, F., Mohd, A.S., Noor, Z.A., Elgomati, H.A.
Published 2017

Variability analysis of process parameters on subthreshold swing in vertical DG-MOSFET device

by Kaharudin, K.E., Salehuddin, F., Hamidon, A.H., Zain, A., Abd Aziz, M.N.I., Ahmad, I.
Published 2017

Electrical characterization of different high-k dielectrics with tungsten silicide in vertical double gate nmos structure

by Kaharudin, K.E., Salehuddin, F., Soin, N., Zain, A.S.M., Aziz, M.N.I.A., Ahmad, I.
Published 2017