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| LEADER |
00000cam a2200000 7i4500 |
| 001 |
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100719s2010 nju eng |
| 020 |
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|a 0130891614 (alk. paper)
|
| 020 |
|
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|a 9780136019282 (alk. paper)
|
| 090 |
0 |
0 |
|a TK7885.7
|b .C548 2010
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| 100 |
1 |
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|a Ciletti, Michael D.
|e author
|
| 245 |
1 |
0 |
|a Advanced digital design with the Verilog HDL
|c Michael D. Ciletti
|
| 260 |
|
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|a Upper Saddle River, NJ
|b Pearson Education
|c c2010
|
| 300 |
|
|
|a p. cm.
|
| 440 |
|
0 |
|a Prentice Hall XILINX design series
|
| 650 |
|
0 |
|a Logic design
|x Data processing
|
| 650 |
|
0 |
|a Verilog (Computer hardware description language)
|
| 999 |
|
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|a 1000131862
|b Book
|c OPEN SHELF (30 DAYS)
|e Tembila Campus
|